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? semiconductor components industries, llc, 2002 january, 2002 rev. 0 1 publication order number: and8078/d and8078/d a simple low-cost non-isolated universal input off-line converter prepared by: roland saintpierre field applications engineer introduction switchmode offline power conversion typically entails a means of galvanic isolation from primary to secondary. in most instances it includes a stepdown high frequency transformer, which aids in the voltage conversion necessary from the high dc bulk voltage generated from the bridge rectifier to the lower output dc voltage required by the end application. if isolation is not a requirement of the application, in which safety can be insured by mechanical means, the additional cost of the transformer and optocoupler can be saved. the circuit describe herein is proposed as a simple and low cost means to convert the ac mains voltage to a lower dc voltage which may be used in a variety different applications which include a preregulator for a linear voltage regulator. circuit description the circuit shown below is a very low cost, universal ac input, nonisolated converter employing a buckboost topology. the simple halfwave rectified ac input provides a dc voltage to the bulk capacitor (c1), which is then converted, to the semiregulated dc voltage required on the output. for this power level an lc filter was chosen to meet conducted emi requirements. this example describes the design and analysis of a converter providing 8.0 vdc at 0.4 a. figure 1. nonisolated universal input buckboost converter employing the 60 khzncp1200 d1 1n4006 r1 2.2 l1 2.2 h 100250 vac 50/60 hz c1 10 f 400 v r2 2.2 c2 10 f 400 v l2 2.2 h q2 2n3904 c3 470 pf ncp1200p60 hv gate is gnd vcc c4 0.01 f 8 2 u1 q1 std2nb60 c5 220 pf 1 kv 5 3 4 1 c6 22 f l3 120 h c7 100 f 10 v 8 vdc @ 0.4 a + c6 680 pf r3 220 d2 1n5924b 9.1 v d3 1n4937 r4 6 http://onsemi.com application note
and8078/d http://onsemi.com 2 ncp1200 at the heart of the converter is the ncp1200 offline currentmode pwm converter ic. this controller features a dynamic selfsupply (dss) that allows it to be powered directly from the high voltage rectified line voltage. this ic also features a currentmode controller with skip cycle capability, an internally set fixed frequency oscillator (available in 40 khz, 60 khz and 100 khz), extremely low noload standby power, and builtin frequency jittering for reduced emi. - + - + - + 250 ns l.e.b. 40, 60 or 100 khz clock overload? fault duration skip cycle comparator 1 v v ref 5.3 v q flipflop dcmax = 80% 110 ma 20 k 60 k 8 k 75.5 k 29 k 1.4 v reset q set uvlo high and low internal regulator hv current source internal v cc 4 3 2 1 current sense fb adj ground drv v cc nc hv 8 7 6 5 figure 2. ncp1200 internal circuit architecture buckboost topology the basic buckboost topology, shown below in figure 3, is typically attributed as an inverting circuit since the output has the reverse polarity of the input voltage. more commonly the isolated version of this converter (flyback) is used. figure 3. buckboost topology pwm the magnetic element in the flyback converter simply replaces the inductor in figure 3 with a coupled inductor with two or more winding and repositions the switch to the low side to facilitate gate drive, which reveals the more common offline circuit topology. figure 4. flyback converter pwm the converter shown in figure 1 is essentially the same topology as figure 3 except that the switching device has been placed on the bottom rail and the polarity of the input and output voltage has been reversed to produce a positive output voltage from a negative input source.
and8078/d http://onsemi.com 3 derivation of the output characteristic equation this converter was designed to operate in discontinuous conduction mode (dcm). as with all switchedmode converter topologies the characteristics equation relating the input to output voltage made be derived from a fundamental analysis of the topological modes of the converter. the modes of the converter are examined by redrawing the circuit for each of the distinct cases of conduction of the active and passive switches. figure 5. topological modes of the buckboost converter in dcm mode i mode ii mode iii in dcm, there are three distinct operating modes. in mode i, the switch is aono and the input source is connected to the inductor, the output load is supported by the output capacitor since the rectifier in this case is reversebiased. during mode ii, the main switch (q1) is turned off and the inductor voltage acts as a source polarity switch and reverses it voltage. this in turns causes d1 to conduct and the load current is supported by the stored energy in the inductor. in the third mode, neither the switch nor diode is conducting since the inductor current has fallen to zero. in equilibrium the volttime product across the inductor during the first two modes must be equal (shaded regions on figure 6), this information can be used to derive the inputoutput voltage characteristic equation that is valid for both continuous and discontinuous conductionmode. vin t on vot off (1) vo vin t on t off (2) idealized converter waveforms for the all the pertinent active and passive devices are shown in figure 6. the average diode current (i d ) is the output load current (io); an expression for the output current may be derived as: io t off ipk 2ts (3) where ts is the switching period, and ipk is given as: ipk vin l t on (4) combining terms and rearranging equation (3) and (4), we can solve the aofftimeo as a function of input voltage ( vin ), switch aontimeo ( t on ), switching period ( ts ), inductance ( l ) and load current ( io ). t off 2tslio vin t on (5) the aofftimeo can also be expressed as a function of the switching period ( ts ), inductance ( l ) and load resistance ( ro ). simply substitute ipk from equation (4) into the equation for io ; equation (3), which yields: io vin t on t off 2tsl (6) solving for | vin| in equation (2) and substituting it into (6) yields: io vo t off 2 1 2tsl (7) rearranging (7) and substituting ro for vo/io , we find that the aofftimeo may be expressed as: t off 2tsl ro (8) another essential parameter of this converter is the duty cycle ( a d ), which is the ratio of aontimeo to the switching period ( t on /ts ). the equation for the duty cycle is by solving for the aontimeo in equation (2), and substituting the result of t off from equation (5): d 1 vin 2voiol ts (9) since, a = t on /ts and (1 a ) is t off /ts , the expression for the dutycycle ( a c ) of a buckboost converter is continuous conduction mode (ccm) is load independent and may be derived from (2) as: c vo vin vo (10)
and8078/d http://onsemi.com 4 figure 6. idealized converter waveforms ipk ipk v in + v o v in v o drain current diode current inductor current drainsource voltage inductor voltage v in t on t off t d t s input stage design a halfwave rectified input stage was selected to reduce cost and overall part count. this basic circuit comprises of a standard recovery rectifier and single high voltage capacitor. the only constraint of this circuit is peaktopeak voltage ripple on the bulk capacitor and its affect on the output. a smaller bulk capacitor will allow higher 120 hz ripple on the dc bulk voltage and depending on the loop dynamics a higher amount of this frequency component on the output voltage. using the technique outlined in [1], we find that a total bulk capacitance of 20 f will suffice for this circuit. please note that a capacitor of with roughly half of this capacitance would have been required had we opted to use a full bridge rectifier. figure 7 shows the pspice simulation results for the bulk capacitor voltage with a halfwave rectified input source at 100 vac/60 hz into the input filter arrangement shown in figure 1 with a constant 4.7 w load (assumes 75% efficiency). the following chart tabulates the results of this simulation for high and low line conditions maximum rated load. table 1. input filter simulation summary vin 100 vac/60 hz 250 vac/50 hz vmin 78.3 v 339 v vmax 112.8 v 352.2 v vavg dc 96.4 v 344.7 v figure 7. simulation plot of the bulk dc capacitor at low line time (ms) 32 36 40 44 48 52 56 60 64 v(vdc) 70 80 90 100 110 120
and8078/d http://onsemi.com 5 dc analysis the expected duty cycle of the converter can be computed over the operating line range using the expressions we derived above. the converter can be expected to operate over a relatively broad range of dutycycles, which span the expected line and load range. at noload and light load conditions, the ncp1200 will enter into a skipcycle mode whereby the input power and peak current limit will be significantly reduced. the inductor value was chosen to maintain dcm operation for all operating conditions. an expression for the critical inductance (inductance value at the border between ccm and dcm) may be derived from solving for l in equation 8: lc vo io (1 ) 2 ts (11) solving the critical inductance equation above for low line conditions (vin = 96.4 vdc) and our load current and output voltage, we find that the desired inductance to remain in dcm must be less than 142 h. using this inductance will cause the converter to operate at critical conductionmode; the operating duty cycle ( a ) at low line is 7.7% ( t on = 1.28 sec). the design value of the inductor in this example was chosen to be 120 h. we can also find that the peak switch and inductor current will stay relatively constant over the line range at our rated load. the peak switch current using an inductance of 120 h (not accounting for circuit losses) is 0.94 a. current sense resistor again using the guidelines from [1], we find that a suitable value for the sense resistor is 1.0 w . the peak switch current limit neglecting the propagation delay of the ncp1200 will be approximately 0.9 v/1.0 w = 0.9 a. this value is confirmed in the simulation results and breadboard example of the circuit, which are discussed in subsequent sections. device selection the only design constraints for the mosfet are its drainsource voltage and drain current ratings. for this design, the minimum vds rating is vin max + vo = 353 + 8 = 361 v, and minimum drain current rating of 1.0 apk. the breadboard example utilizes a stmicro std2nb60e, which has a vds rating of 600 v, id = 2.2 a with an rdson of 3.6 w . the output rectifier must be rated to handle the average output load current of 0.4 a, a peak current of 0.9 a, and a breakdown voltage of 293 v. a low cost leaded ultrafast rectifier (1n4937) was chosen, which is rated at 600 v/1.0 a. output voltage regulation the output voltage of this converter is regulated using a zener diode and npn transistor. the output voltage is the zener voltage + the vbe voltagedrop of the transistor. a more precise output voltage can be achieved using a tl431, which will also allow traditional loop compensation techniques. figure 8 depicts a possible implementation of the tl431 shunt regulator for precise output voltage regulation. figure 8. tl431 implementation for precise output voltage regulation ncp1200p60 hv gate is gnd vcc 8 2 mtp1n60e 220 pf 1 kv 5 3 4 1 22 f 120 h 100 f 8 vdc @ 0.4 a + 1n4937 6 3 k 680 pf 200 k tl431 18.7 k 8.45 k 0.01 f
and8078/d http://onsemi.com 6 compensating the zener regulator can be achieved by adding an rc network from collector to base of the transistor and/or adding a parallel capacitor to the resistor which is between the zener and transistor base. this resistor not only sets the bias conditions for the transistor and zener, but also sets the openloop gain of the circuit. the additional capacitor across the basecollector of the transistor will help roll off its inherent high frequency gain and more importantly the converter. simulation results the following plots are results of a transient simulation performed on pspice. the simulation schematic is shown in figure 9, followed by plots of the output voltage, drainsource voltage, current sense resistor voltage and inductor current. figure 9. pspice simulation schematic vin v1 + 353 hv vout d19 d1n5242 c3 680 p r6 220 r5 20 r4 0.1 c1 100 f, ic = 8 d7 d1n4937 2 1 l1 120 h r1 1 c4 1 n c6 470 p fbe q1 q2n3904 vfb isns 3 0 4 2 1 adj ncp1200 u1 ncp1200 fs = 60 k 8 6 5 gate m1 mtd1n60e c5 220 p r2 1 0 vcc c2 22 f, ic = 12.1 r3 0.2
and8078/d http://onsemi.com 7 figure 10. simulation results output voltage, current sense voltage, and inductor current vin = 96.4 vdc, ro 20 330 340 350 360 370 327 380 i(l1) v(isns) v(vout) 0v 0.2v 0.4v 0.6v 0.8v 1.0v 1 6.5v 7.0v 7.5v 8.0v 2 time ( s) figure 11. simulation results mosfet drainsource voltage vin = 96.4 vdc, ro 20 370 375 380 385 390 395 400 405 410 415 v(hv,isns) 0v 20v 40v 60v 80v 100v 120v time ( s)
and8078/d http://onsemi.com 8 figure 12. simulation results output voltage, current sense voltage, and inductor current vin = 353 vdc, ro 20 430.0 440.0 450.0 460.0 470.0 423.2 7.5v 8.0v 8.5v 9.0v 1 0v 0.5v 1.0v 0.2v 1.4v 2 i(l1) v(isns) v(vout) time ( s) figure 13. simulation results mosfet drainsource voltage vin = 353 vdc, ro 20 380.0 384.0 388.0 392.0 396.0 400.0 404.0 408.0 412.0 416.0 0v 100v 200v 300v 380v time ( s)
and8078/d http://onsemi.com 9 actual hardware oscillographs and performance summary the circuit shown in figure 1 was built to validate the analysis and verify operating specifications. the following plots show the output voltage at full load and noload, as well as the drainsource voltage, current sense resistor voltage, and bulk dc voltage at full load. a figure showing regulation voltage over the line and load range is shown in figure 18. figure 14. hardware oscillograph current sense resistor voltage vin = 100 vac/60 hz, ro 20 figure 15. hardware oscillograph vd voltage waveform vin = 100 vac/60 hz, ro 20 figure 16. hardware oscillograph output voltage vin = 100 vac/60 hz, ro 20 figure 17. hardware oscillograph bulk dc voltage with respect to circuit gnd vin = 100 vac/60 hz, ro 20
and8078/d http://onsemi.com 10 figure 18. hardware operating characteristics (line/load regulation) 7.75 7.85 7.95 8.05 8.15 8.25 8.35 8.45 8.55 8.65 8.75 0 50 100 150 200 250 300 350 400 450 500 550 output voltage (vdc) load resistance ( ) 400 ma 200 ma 10 ma 50 ma 2.0 ma 85 vac/60 hz 120 vac/60 hz 240 vac/60 hz 265 vac/60 hz pcb the complete bill of material and pcb component silkscreen and artwork layers are shown for the ncp1200 design example. the pcb is a single sided cem1 chosen for its low manufacturing cost. bill of material ref des part no. part description manufacturer geometry r1, r2 2.2 1/4 w metal film leaded axial r3 220 , 1/8 w metal film leaded axial r4 1.0 , 1/2 w axial c1, c2 urs2g100mha 10 f, 400 v, alum. electrolytic nichicon 16 x 15 mm c3 470 pf, 50 v, monolithic ceramic disc c4 0.01 f, 50 v, monolithic ceramic disc c5 220 pf, 1.0 kv, monolithic ceramic disc c6 uhc1c220mdr 22 f, 16 v, alum. electrolytic nichicon 5 x 7 mm c7 uhc1c101mdr 100 f, 16 v, alum. electrolytic nichicon 6.3 x 11 mm l1, l2 913028 2.2 h, 395 ma, rdc = 0.4 , axial leaded molded rf choke jw miller magnetics www.jwmiller.com axial l3 120 h, 1.5 a d1 1n4006 standard recovery 800 v, 1.0 a on semiconductor case 5903 d2 1n5924b zener voltage regulator, 9.1 v, 3.0 w on semiconductor case 5904 d3 1n4937 fast recovery diode, 600 v, 1.0 a on semiconductor case 5903 q1 std2nb60 nchannel mosfet, 600 v/3.6 stmicroelectronics ipak q2 2n3904a general purpose, npn, 30 v/100 ma on semiconductor to92 u1 ncp1200 offline current mode pwm controller ic on semiconductor dip8
and8078/d http://onsemi.com 11 figure 19. pcb silkscreen and artwork tp3 tp5 tp9 tp10 tp11 tp12 tp13 w4 w3 d3 c7 c6 tp6 l3 r3 d2 c2 tp4 tp6 tp1 tp2 c1 w2 w1 d1 r1 l1 l2 r2 r4 c5 c4 tp7 q2 q1 u1 jp1 c5 c3 ons 1001 rev a alternate embodiment the circuit shown in figure 1 is a nonisolated offline converter with a key deficiency is some applications, in the fact that both the line (hot) and neutral ac inputs are switched. the mosfet drain (switching node) is connected to the neutral and the line (hot) is tied to a rectifier, necessary to develop the required dc voltage for conversion. this configuration has potentially serious safety issues. for safety, the circuit shown below maintains a ground referenced neutral line and which is common to the output return. ncp1200 hv cs drv gnd vcc 8 2 5 3 4 + (gnd) 6 + nuetral ac + + fb line (hot) figure 20. in this circuit transformation, the mosfet source is tied to the line and the neutral is at ground potential. in order to regulate the output voltage, an optocoupler must be used in the feedback loop to overcome differences in the commonmode voltage potentials between the output and fb pin of the control ic. this is due to the fact that the ncp1200 is now referenced to the rectified ac line (hot).
and8078/d http://onsemi.com 12 conclusion this paper detailed the design and analysis, including device selection criteria, for a nonisolated offline buckboost converter. the ncp1200 series offers suf ficient flexibility to configure this topology for various output voltage and power requirements. alternatively, the ncp105x series of offline gatedoscillator ics may also be used in this topology. figure 21. adaptation with the ncp1052b d1 1n4006 r1 2.2 l1 2.2 h 100250 vac 50/60 hz c1 10 f 400 v r2 2.2 c2 10 f 400 v l2 2.2 h q2 2n3904 ncp1052b control switch gnd vcc c4 0.01 f 2 u1 5 3, 68 c6 22 f l3 120 h c7 100 f 10 v 8 vdc @ 0.1 a + c6 680 pf r3 220 d2 1n5924b 9.1 v d3 1n4937 1 the ncp105x series feature an onchip 700 v power switch, a unique dualedge gated oscillator for extremely fast loop response, high voltage startup and operation, frequency dithering for reduced emi filtering, and an internally set frequency options (44, 100 and 136 khz). the distinct advantage of this ic in this converter is the lower overall part count since the mosfet and current sensing resistor are internalized. the ncp105x series and its derivatives are offered in a wide variety and combinations of switching frequency and peak current limits. in either case whether it be a ncp1200 or ncp105x, the key features and attributes of these ics make them uniquely suitable to configure this topology for very low cost offline power conversion. acknowledgments the author would like to acknowledge douglas k. thomson, sr. design engineer with abb automation inc., in raleigh, nc, for inspiring this application note as well as the insightful conversions relating to this topic. references 1. an8023/d, aimplementing the ncp1200 in lowcost ac/dc converterso, christophe basso, october 2000. 2. an8038/d, aimplementing the ncp1200 in a 10w ac/dc wall adaptero, christophe basso, october 2000. on semiconductor and are trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scill c data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthori zed use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. publication ordering information japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1410031 phone : 81357402700 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. and8078/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com n. american technical support : 8002829855 toll free usa/canada

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